1. Field of the Invention
The invention relates in general to a voltage stabilizer circuit, and more particularly to a voltage stabilizer circuit applied to a power management system.
2. Description of the Related Art
Conventionally, low dropout voltage (LDO) regulator circuits are applied to various power management systems, such as a battery system of a handheld electronic device. FIG. 1 is a circuit diagram showing a conventional low dropout voltage (LDO) stabilizer 10. Referring to FIG. 1, for example, the LDO stabilizer 10 includes an error operational amplifier OP1, a transistor T1, and resistors R1 and R2, wherein the negative input end of the error operational amplifier OP1 receives a reference voltage Vrf. The transistor T1 and the resistors R1 and R2 constitute a feedback circuit for feeding an output voltage Vx of the error operational amplifier OP1 back to the positive input end of the error operational amplifier OP1 so that a feedback voltage substantially approaching the level of the reference voltage Vrf can be provided.
Conventionally, a high-capacitance load capacitor CL and an equivalent series resistor (ESR) RL have to be disposed at the output end of the LDO stabilizer 10 so that the LDO stabilizer 10 can operate stably. However, the load capacitor CL is implemented by a larger integrated circuit (IC) area or a discrete element. Thus, the conventional LDO stabilizer 10 has the drawback of the larger circuit area and the higher manufacturing cost. If the load capacitor CL is omitted, the LDO stabilizer 10 cannot operate stably.